(1) Field of the Invention
This invention relates to the fabrication processes use to create semiconductor devices, and more specifically to methods used to create metal via structures, used to interconnect overlying and underlying metallization levels.
(2) Background of the Invention
The semiconductor industry is continually striving to increase the performance of semiconductor devices, while still maintaining, or decreasing, the manufacturing cost of these same semiconductor devices. These objectives have been successfully addressed by the ability of the semiconductor fabrication community to successfully create silicon devices with specific sub-micron features. The advent of micro-miniaturization, or the use of sub-micron features, has largely been accomplished by advances in several semiconductor fabrication disciplines, specifically photolithography and anisotropic dry etching. The development of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have resulted in sub-micron images in photoresist layers being routinely obtained. In addition similar advances in dry etching, or reactive ion etching, (RIE), have allowed the sub-micron images in photoresist layers, to be successfully transferred to underlying materials, used for the construction of silicon devices. The use of sub-micron features results in decreases in parasitic capacitances, as well as resistance decreases, both providing performance benefits. In addition the smaller features allow a greater number of smaller silicon chips to be obtained from a specific size starting wafer, thus reducing the manufacturing cost for individual chips.
The use of semiconductor chips, fabricated with sub-micron features, does however create specific areas of concern, not encountered with semiconductor chips, fabricated with less aggressive designs. For example, metal filled via holes, used to interconnect metallization levels, are more difficult to form when using sub-micron designs. Via holes, with sub micron diameters, are also difficult to fill with conventional metallization deposition techniques, such as sputtering or evaporation. The high aspect ratio of the via hole, that is the depth of the via, divided by the diameter of the via opening, requires a low pressure chemical vapor deposition, (LPCVD) process for adequate via hole filling. Since it is difficult to deposit aluminum based metallizations, using LPCVD, the semiconductor industry has used LPCVD tungsten to fill these high aspect ratio via holes. However even with the use of LPCVD tungsten, several shortcomings still exist. For example since the LPCVD fill of a via hole proceeds by tungsten depositing on the sides of the via hole, a seam or imperfection can exist in the center of the tungsten filled via, at the point of convergence of the depositing layers. This seam, when subjected to RIE etch back processes, used to remove unwanted tungsten from areas of the silicon device, other than the via hole, can evolve into a larger seam or defect, making it difficult for subsequent overlying metallizations to successfully cover. Thus overlying metallizations, thin in areas overlying the enlarged seam, may experience higher current densities than desired, and possibly resulting in electromigration failure.
This invention will describe a process for creating metal vias, or studs, using a chemically vapor deposited tungsten layer, to fill a narrow contact hole, or via hole opening, in a dielectric layer. However, to avoid expanding the existing seam in the tungsten fill, a photolithographic and reactive ion etching procedure, is used to remove unwanted tungsten from areas outside the contact or via hole vicinity. These process steps, unlike a blanket etchback, will not allow the narrow seam in the tungsten fill to evolve into a more deleterious fault, in areas where the via is directly over the contact hole. In addition this approach results in a raised, or extended, tungsten plug structure, that is the top surface of the tungsten plug is higher then the top surface of the dielectric layer, that the contact hole was formed in. A first level interconnect metallization structure, is formed from patterning a metal layer, overlying the extended tungsten plug, and when subjected to subsequent insulator deposition and planarization processes, allow successful contact between overlying second level, and underlying first level metal interconnect structures, without the creation of a via hole. Prior art, such as Cote, et al, in U.S. Pat. No. 5,312,512, suggest filling holes in a dielectric layer with a metal, followed by a chemical mechanical polishing removal procedure. The concept described in this invention, now disclosed, is to create a raised, or extended metal pattern, using a masked, etchback procedure, with the raised, or extended metal structure to be used to allow contact to subsequent overlying interconnect metallization structures, without via hole formation procedures.